The present invention relates to semiconductor devices and their fabrication. More particularly, the present invention relates to a method of forming a gate conductor structure having a cross-diffusion barrier for inhibiting diffusion of a dopant between adjacent devices.
FIGS. 1 and 2 illustrate a complementary metal oxide semiconductor (“CMOS”) transistor pair in accordance with the prior art. The CMOS transistor pair includes an n-type conduction channel field effect transistor (“NFET”) 10 and a p-type conduction channel field effect transistor (“PFET”) 20. A polyconductor 30, consisting essentially of a polycrystalline semiconductor such as polysilicon, includes a gate 32 of the NFET, a gate 34 of the PFET and a conductor extending over a trench isolation region 25 between the NFET and the PFET. Ideally, the gate 32 of the NFET would have an n+ dopant concentration throughout and no part of the gate 32 would have a p+ dopant concentration. Ideally, the gate 34 of the PFET would have a p+ dopant concentration throughout, and no part of the gate 34 would have an n+ dopant concentration.
However, during fabrication of the CMOS transistor pair, the diffusion of dopants in the directions indicated by the arrows 38 can cause portions of the gates 32, 34 to have both n+ and p+ dopant concentrations. A portion 40 of the polyconductor overlapping the gates 32, 34 has both n+ and p+ dopant concentrations.